Method for encoding/decoding digital data transmitted through a serial link, particularly of the 8B/10 type, and device for implementing same

ABSTRACT

The invention concerns a method and a device for encoding/decoding digital data transmitted through a serial link (I s ), particularly of the so-called “8B/10B” type. The full encoded binary word includes 8 data bits (A . . . H) and a 2-bit label (X 1 X 2 ). The logical state of a center bit triplet (CDE) of the byte is detected. When all of the bits are in the same logical state, “0”) or “1,” the center bit of the triplet (D) is inverted ( 4 ) prior to transmission. Otherwise, the byte is transmitted as is. The label (X 1 ,X 2 ) is forced ( 7 ) to the logical configuration “10 ” when there is a bit inversion, and to “01” in the opposite case. Upon decoding, this configuration is tested and the center bit received is selectively inverted as a function of the result of the test. In a preferred variant, the method also includes tests of the label and the triplet after decoding, when there has been a bit inversion in the encoding. The device comprises logical circuits ( 3, 4, 7 ) based on inverters and “AND,” “OR” and “EXCLUSIVE-OR” logic gates.

[0001] The invention concerns a method for encoding/decoding digitaldata transmitted via serial links.

[0002] It particularly concerns an encoding/decoding method of theso-called 8B/10B type, the letter “B” being the abbreviation for “bit.”

[0003] It applies more particularly to serial links of the high speedshort distance type.

[0004] The invention also concerns a device for implementing the method.

[0005] Within the context of the invention, the term “digital data”should be understood in its most general sense. It includes the conceptsof messages, binary words, etc., and generally all sequences of binaryelements or bits, the length of which is determined by the particularapplication envisaged.

[0006] Transmissions of the aforementioned byte are specificallycharacterized by the fact that they are not associated with a clock,unlike, for example, parallel transmissions of digital data. In thelatter case, all the bits that compose a binary word, for example, aretransmitted simultaneously, through as many physical links. It followsthat in the case of a serial link, it is necessary to adopt measures forretrieving clock information in the receiver.

[0007] Another constraint that must generally be obeyed is the need toguarantee a pre-established transition rate among all the bitsconstituting a binary sequence. Typically, it is desirable to obtain anaverage rate of 30% for a 1000-bit sequence.

[0008] Yet another constraint relates to the setting of a particularparameter known as “Maximum Run Length”(“MRL”), or the maximum number ofsuccessive bits that can remain at the same logical value, “0” or “1.”

[0009] In the prior art, in order to meet satisfy these requirementssimultaneously, so-called “DC balanced” codes are most often used, i.e.codes that do not induce any DC component, at least within apre-established time interval.

[0010] One of the characteristics of these codes is that theyincorporate control and/or command words that specifically make itpossible to retrieve clock signals on the receiving end of the binarysequences sent, but also control the sending and receiving procedures ofthe devices located at both ends of the chain (transmitter andreceiver).

[0011] However, while this type of code makes it possible to solve, atleast partially, the problems mentioned above, this technique is notwithout its drawbacks.

[0012] In particular, these codes involve the use of highly complexcircuits. In practice, they are essentially used for “long distance”links.

[0013] One need that has arisen in recent information technologies istied to the increase, in a single device or even in a single electroniccircuit card, in the number of asynchronous serial links. For example,in a single device, there are card-to-card links. In a single card,there are links between modules or integrated circuits (“chips”). Toillustrate the concept, the number of links can reach several tens ofunits, for example typically 72 asynchronous serial links between two“chips.”

[0014] In this context of the preferred application of the invention,the essential characteristic of the transmissions in question is thatthey take place over short distances—a few centimeters or even a fewmillimeters. Moreover, current technologies make it possible to use veryhigh frequencies, commonly higher than 2.5 Mbps.

[0015] It is understood that, under these conditions, the solutions ofthe prior art, particularly the use of so-called “DC balanced” codesinvolving a high degree of complexity in terms of electronic circuits,cannot be satisfactory, especially since the proximity of the circuitsand/or modules does not entail incorporating command words into thebinary sequences transmitted.

[0016]FIG. 1, attached to the present specification, schematicallyillustrates an exemplary architecture of asynchronous serial links, 11and 12, between two electronic circuit cards, C₁ and C₂ respectively,located in proximity to one another in a single unit 1. A thirdelectronic circuit card, which will be called a “management card” CMtransmits control words MtC, for example via a single bus, to the twoelectronic circuit cards C₁ and C₂, which are in close connection.

[0017] While it is not mandatory, for short distance links, toincorporate command words into the binary sequences transmitted, it isnonetheless necessary, no matter what encoding method is used, to meetall of the other requirements mentioned.

[0018] It is also important for the encoding process not to propagatethe errors if one or more bits are set erroneously (inversion of theirlogical states). This requirement is particularly important whenimplementing means for detecting and correcting errors (codes known as“ERC” or “Error Recovery Codes”). Upon reception, the message decodedand processed by the “ERC” circuits should be identical to the originalmessage sent, even if errors occur during transmission.

[0019] The object of the invention is to eliminate the drawbacks of thedevices and systems of the prior art, some of which have beensummarized, while meeting the needs that continue to arise.

[0020] In particular, the method according to the invention makes itpossible to greatly simplify the encoding circuits required for itsimplementation, without deteriorating the quality of the transmissions.

[0021] More particularly, but not exclusively, the preferredapplications of the invention concern an encoding of the so-called8B/10B type. As indicated, the letter “B” stands for “bits.” This typeof code is particularly advantageous because it makes it possible tohandle bytes comprising exactly 8 bits, which will be qualified as databits, since they convey information. The byte is completed by 2additional bits, in specific logical states “1” or “0.” Such codes areintrinsically known. An example may be found in U.S. Pat. No. 5,025,256A (International Computers Limited).

[0022] The main subject of the invention is a method forencoding/decoding digital data to be transmitted through a serial link,said digital data comprising a first so-called data bit sequence and asecond so-called “label” bit sequence, characterized in that, said firstand second sequences having first and second given bit lengths, itincludes at least one encoding phase comprising at least a step forchecking at least one slice of at least two consecutive bits, each ofsaid slices being located in a predetermined area of said first bitsequence, so as to create a partitioning of the latter into parts ofapproximately equal length, said check consisting of performing a testto determine whether the consecutive bits of each of said slices are inthe same logical state, “0” or “1,” a second step consisting of settingthe bits of said second sequence to predetermined logical stateconfigurations in one-to-one relation with the result of said test, anda step for inverting at least one bit of said slices when the result ofsaid test is positive and for transmitting said first bit sequencewithout any modifications when the result of said test is negative.

[0023] Another subject of the invention is a device for implementingthis method.

[0024] The invention will now be described in greater detail byreferring to the attached drawings, in which:

[0025]FIG. 1 schematically illustrates an architecture of asynchronousserial links between two electronic circuit cards;

[0026]FIG. 2 illustrates a binary word encoded according to the 8B/10Bmethod;

[0027]FIGS. 3A and 3B illustrate exemplary circuits for detecting aparticular configuration of the word of FIG. 2, usable in an encoder forimplementing the method according to the invention;

[0028]FIG. 4 illustrates an exemplary embodiment of a complete encoderaccording to the invention incorporating one of the circuits of FIGS. 3Aor 3B;

[0029]FIG. 5 illustrates an exemplary detection circuit usable in adecoder for implementing the method of the invention for a word encodedby the circuit of FIG. 4;

[0030]FIGS. 6 and 7 illustrate exemplary circuits for detecting errorsin the encoded words received by the decoder; and

[0031]FIGS. 8A and 8B illustrate words encoded according to theinvention, of any length.

[0032] We will now describe in greater detail a preferred exemplaryembodiment of the method for encoding digital data transmitted throughan asynchronous serial link according to the invention. First of all, toillustrate the concept without in any way limiting the scope of theinvention, we will consider the context of the preferred application ofthe invention, i.e. an encoding of the 8B/10B type.

[0033]FIG. 2 illustrates a binary word with 10 bits, labeled b₁, throughb₁₀. The positions of bits 20, b₁ through b₈, which are referenced “A”through “H,” constitute the data bits per se (byte). The positions Athrough H can each assume the logical states 1 or 0.

[0034] The two additional bits 21, b₉ and b₁, are referenced “X₁” and“X₂” in FIG. 2. These bits can be called “label” or “pattern” bits. In apreferred embodiment, these bits are simply concatenated with the eightother bits of the byte 2. The logical state, 1 or 0, of the two bits b₉and b₁₀ depend on the logical values of at least some of the other bitsb₁ through b₈ of the word 2, and obey rules, which will be specified.

[0035] In general, the eight bits b₁ through b₈ of the byte 20 aretransmitted as is, and the label bits 21 then assume the logical state“01” (b₉b₁₀). The label 21 can be concatenated either in front of orbehind the bits of the byte 20, the bit b₁ (“A”) being assumed to thefirst bit of the byte 20 to be sent.

[0036] The full binary word 2 therefore has the logical configuration“ABCDEFGH01”.

[0037] On the other hand, in the case where three consecutive bits ofthe central area of the byte 20 are in the same logical state (0 or 1,respectively), the center bit of this area is inverted in order toincrease the transition density. Either the bit triplet b₃b₄b₅(positions “CDE”) or the bit triplet b₄b₅b₆ (positions “DEF”) arechosen. The center bit is therefore the bit b₄ (position “D”) in thefirst case or the bit b₅ (position “E”) in the second case. The choiceof the three bits is made a priori once and for all for a givenembodiment.

[0038] In this case, the label 21 has been given to the logicalconfiguration “10” (b₀b₁₀ ).

[0039] For example, if the byte 20 has the logical value “11111000,” thefull word is encoded as follows: “11101000-10,” it being understood thatthe dash is simply used to indicate the separation between the byte 20and the label 21, but it does not physically exist, the two bit stringsbeing sent one after the other, without any time interval separatingthem a priori. It is noted that the bit b₄ (position “D”) is invertedrelative to its original logical value.

[0040] Using the encoding method according to the invention, thefollowing characteristics are obtained:

[0041] minimum transition frequency: 2 for 10 bits, or 20%;

[0042] maximum number of consecutive identical bits or “max run length”:6, when the non-transition detection involves 3 consecutive bits of acenter area (see FIGS. 3A and 3B below) and 5, when this same detectioninvolves only 2 bits (see FIG. 7 below); and

[0043] non-propagation of the errors and retention of the “ERC” codestransmitted.

[0044] In essence, when it comes to this last characteristic, if thedata (byte 20) contains one or more error(s), this error or errors is(are) simply transmitted. By contrast, in the case of a transcodingaccording to the prior art, there is a real risk of propagation of theerrors.

[0045] Furthermore, the device required to obtain the encoding is verysimple to produce.

[0046]FIG. 3A illustrates a first exemplary basic embodiment of an “AND”logic gate 30 and two “OR” logic gates 31 and 33, and an inverter 32.

[0047] In FIG. 3A, it is assumed that the three center bit positions(“CDE”) have been retained. The “AND” 30 and “OR” 31 logic gates havethree inputs, each receiving one of the three signals of the triplet“CDE.” The output of the “OR” logic gate 31 is connected to the input ofthe inverter 32. The output of the inverter 32 is connected to a firstinput of the “OR” logic gate 33. A second input directly receives theoutput from the “AND” logic gate 30. As illustrated in FIG. 3A, the“AND” logic gate 30 detects the simultaneous appearance of bits in thelogical state “1” (output from this gate in the logical “1” state) andthe “OR” logic gate 31 detects the simultaneous appearance of bits inthe logical state “0” (output from this gate in the logical “0” state).In both of these cases, the “OR” logic gate 33 receives a logical “1” ineither of its inputs. The output S of this gate in this case becomes alogical “1,” which indicates that the three center bits b₃b₄b₅(positions “CDE” in the example) are in the same logical state (either“111” or “000”). The application of well known rules of combinationallogic shows that, in all other cases, the output S is in the “0” logic,which indicates that these three center bits are not in the same logicalstate and that the byte 20 can be transmitted as is.

[0048]FIG. 3B illustrates another exemplary embodiment of a logicalcircuit 3′ that fulfills the same function as the circuit 3 of FIG. 3A,i.e., the testing of the bits of the triplet in the same logical state.The circuit is constituted by two “EXCLUSIVE-OR” logic gates with twoinputs 30′ and 31′, the first of which receives in its inputs the bitsin the positions “C” and “D” (or “D” and “E” if the triplet “DEF” hasbeen chosen”), the second of which receives in its inputs the bits inthe positions “D” and “E” (or “E” and “F” if the triplet “DEF” has beenchosen). The outputs of the “EXCLUSIVE-OR” gates 30′ and 31′ aretransmitted to the two inputs of an “OR” logic gate 33, which plays arole similar to the gate with the same reference in FIG. 3A, whoseoutput is referenced S. However, in the case of the circuit of FIG. 3A,the output S delivers a signal in the logical state “0” for aconfiguration in which all the bits of the input triplet are in the samelogical state (either “111” or “000”). If the output signal of thisinverter must have the logical state “1” for this same logicalconfiguration, the “OR” gate 33 must be followed by an inverter (notrepresented).

[0049] The output signal S is used to drive the inversion of the bit b₄(position “D”) or b₅ (position “E”), if necessary.

[0050] We will now describe an exemplary complete encoding circuitaccording to the invention and its auxiliary circuits in reference toFIG. 4.

[0051] It is assumed that the byte 21 is initially stored in a register5 or any other similar element (“JK” type toggles, RAM positions, etc.).The positions “A” through “H” are stored in eight cells of this register5, or 5A through 5H. The outputs of the center cells 5C through 5E (forexample) are transmitted to the inputs of the circuits 3 (FIG. 3A or 3′,FIG. 3B), which can be called detector circuits. With the exception ofthe output of the cell 5D (position “D”) the outputs of the other cells5A through 5C and 5E through 5H are also transmitted to thecorresponding inputs of the cells 6A through 6C and 6E through 6H of asecond register 6. It follows that the positions A through C and Ethrough H are simple copies of the corresponding positions of theregister 5. On the other hand, the output from the cell 5D (position“D”) is transmitted to the input of the cell 6D via a logic gate of the“EXCLUSIVE-OR” type 4. The latter therefore receives in a first inputthe output of the cell 5D and in a second input the output S of thedetector circuits.

[0052] The storage position of the cell 6D in the register 6 isreferenced D′, since it is no longer a simple copy of the position D. Ifthe output S is in the logical state “0”, “D” and “D”′ are identical(both in the logical “0,” for example). That is the general case. On theother hand, if the circuits 3 detect three consecutive bits in the samelogical state (see FIG. 3A), the output S changes to the logical “1” andthe corresponding bit at “D” is inverted.

[0053] In the example illustrated in FIG. 4, the register 6 includes twoadditional cells 6X₁ and 6X₂, designed to store the label bits(positions referenced X₁ and X₂). These bits can be generated simplyfrom the output S. The latter need only be directly connected to theinput of the first additional cell 6X₁, and via an inverter 7, to theinput of the second additional cell 6X₂.

[0054] In the general case, S is in the logical state “0.” It followsthat X₁ is in the logical state “0” and X₂ is in the logical state “1”because of the inverter 7. When S is in the logical state “1,” thesituation matches the preceding one, i.e. “10.”

[0055] Once encoded, the full encoded binary word 2 (FIG. 2: byte 20 andlabel 21) is emitted and transmitted through a serial link l_(s) to areceiving element (not represented). The circuits required for theproper transmission of the binary word 2 depend on the preciseapplication envisaged and are intrinsically well known to one skilled inthe art. It is unnecessary to describe them further.

[0056] On reception, the inverse process must be executed. If the label21 has the logical configuration “01,” it means that there has not beenany encoding per se. The byte 20 can be accepted as is, without aninversion of the central bit b₄ (position “D”). On the other hand, ifthe configuration is “10,” it means that the central bit must beinverted.

[0057] The FIG. 5 schematically illustrates an exemplary embodiment of alogical circuit 8 that allows both the necessary detection and theselective inversion operation. This circuit 8 comprises an “AND” logicgate 80, one input of which 800 is inverting and the other of which 801is direct, and that receive the label bits X₂ and X₁ respectively. Theoutput of this “AND” logic gate 80 is transmitted to a first input 810of an “EXCLUSIVE-OR” logic gate 81, which receives in a second input 811the transmitted bit corresponding to the position “D′.” By applying therules of combinational logic, it is easy to see that the outgoing bit(position “D”) of the logic circuit 8 is not modified if theconfiguration “X₁X₂” is “01” and is inverted if the configuration is“10.”

[0058] The word available in the receiving element, in particular the“usable” part corresponding to the information byte 20, is thencorrectly reconstituted.

[0059] In a first additional variant of the method according to theinvention, it is also possible to verify certain errors associated withthe label 21. In essence, in the example described, it can only have thelogical configurations “01” and “10.” The configurations “00” and “11”are therefore not possible, and indicate that this label 21 contains anerror. A simple logical circuit, similar to the one in FIG. 3A, forexample, makes it possible to detect these two configurations. Insteadof using “AND” logic gates with three inputs (FIG. 3A: 30 and 31), logicgates with two inputs are used. The latter receive the bits from thepositions “X₁” and “X₂.” With this exception, the configuration of theerror detection circuit in the label 21 can be identical to that of thecircuit of FIG. 3A. The output of the “OR” logic gate (FIG. 3A: 33) inthe logical state “1” indicates an error. In essence, to obtain thisresult, it is necessary for the bits in the positions “X₁” and “X₂” tobe in the same logical state, “1” or “0.”

[0060] It may also be seen that a dual error in the label 21 translatesinto a single error in the data part (byte 20), hence into an errorreduction and not a propagation.

[0061] In a second variant of embodiment, an additional check isadvantageously performed on the data bits (byte 20). In essence, if thelabel configuration (“10”) has caused the inversion of the center bit onreception (for example in the position “D”), three center bits(positions “CDE”) must be in the same logical state “000” or “111.”Either of these configurations can be detected very simply.

[0062] The logical circuit of FIG. 6 illustrates an exemplary circuit 8a that allows this detection. In practice, the circuit 8 a can beconstituted by the association of an “AND” logic gate 80 a with a directinput 801 a and an inverting input 800 a that receive the bits frompositions “X₁” and “X₂,” and a logical circuit 81 identical to that ofFIG. 3A (or 3B) for example. In essence, the latter should deliverthrough its output, as in the case of FIG. 3A (or 3B), a signal in thelogical state “1” if, and only if, all of its inputs are in the samelogical state “1” or “0.” The logic gate 80 a detects the logicalconfiguration “10” of the bits from positions “X₁X₂” and delivers, inthis case, a signal in the logical state “1.” These two output signalsare compared by means of an “EXCLUSIVE-OR” 82 a, which receives themthrough its inputs 820 a and 821 a, and which delivers through itsoutput S′ a signal in the logical state “0” if, and only if, its twoinputs are in the same logical state “1” or “0”, and in the logicalstate “1” in all other cases, which indicates that there is an error. Inessence, the two inputs in the logical state “1” indicate that the bitsof the positions “CDE” are all in the same logical state (“1” or “0”)and that there has been an inversion (configuration of “X₁X₂”=“10”), andthe two inputs in the logical state “0” indicate that the bits in thepositions “CDE” are in different logical states and that there has notbeen an inversion (configuration of “X₁X₂”=(“01”). These two casesindicate, a priori, that there are no errors.

[0063] It is noted that the logic gate 80 a can be omitted. In fact, itis enough to also transmit the output from the logic gate 80 (FIG. 5) tothe input 820 a of the “EXCLUSIVE-OR” logic gate 82 a, which constitutesan additional simplification.

[0064] In yet another variant of embodiment according to the invention,one simply verifies that there is no transition between two successivecenter bits, for example the bits b₄ and b₅ (positions “D” and “E”),referring again to FIG. 2. These two positions should be set in advance.

[0065]FIG. 7 illustrates an exemplary embodiment of a logical circuit 9that makes it possible to obtain such a detection. This circuit isproduced by means of a single “EXCLUSIVE-OR” logic gate 90 with twoinputs 900 and 901. In the example described, the bits in the positions“D” and “E” are transmitted to these inputs. The state of the output S″of the circuit 9 makes it possible to detect the absence or the presenceof transitions between the bits in the positions “D” and “E.”

[0066] Up to this point in the description, it has been assumed that the“useful” segment of the word, i.e. the informational data, occupies onebyte and that the context is that of the preferred application of theinvention, i.e. so-called 8B/10B encoding.

[0067] However, as indicated, the method according to the invention isnot limited to this application alone. The encoded word and theinformational data part can naturally be of different lengths,particularly longer lengths.

[0068]FIG. 8A illustrates, in a general way, a word to be encoded 2′with a structure according to the invention. The informational date 20′occupies a sequence with an arbitrary length of m bits and the label 21′occupies a sequence with a length of p bits. In order to ensure, inparticular, a “Maximum Run Length” (“MRL”), or predetermined maximumnumber of successive bits that can remain at the same logical value “0”or “1,” it is necessary to monitor the configuration of one or moreslice(s) of n consecutive bits in predetermined areas of the sequence20′.

[0069]FIG. 8A represents two bit slices 20′a and 20′b. The length ofeach of the slices is at least two consecutive bits. The MRL parameterdepends on the number of bits monitored and the distribution of theslices. It is advantageous to have them equally distributed in the m-bitsequence (informational data 20′), or at least approximately equallydistributed.

[0070] This way, the slices partition the m-bit sequence (informationaldata 20′) in an approximately even fashion. The slices 20′a and 20′b aretherefore located (at least approximately) at one-third and two-thirdsof the n-bit sequence, the latter being partitioned into three parts ofapproximately the same length.

[0071] Similarly, if there are three slices (example not represented),they will be located at approximately at one-quarter, one-half andthree-quarters of the m-bit sequence, the latter being partitioned intofour parts of approximately the same length.

[0072] Finally, if t is the number of slices monitored, the number ofextra bits (label 21′) is equal to p, with p≧t.

[0073] By choosing p=t+1, it is possible to guarantee at least onetransition in the label 21′. This configuration constitutes a particularcase, which has just been described in detail for an encoding of the8B/10B type. This systematic transition can serve as a reference pointfor the equal distribution of the partitioning of the slices.

[0074] By choosing p=t+2, it is possible to guarantee at least twotransitions in the label 21′.

[0075] The number of transitions increases in correlation to the valueof p. Such a solution is advantageously applied when the number ofslices, and hence the value of p, is high.

[0076]FIG. 8B illustrates the most general case. The word 2″ comprises,as before, a data sequence 20″ of m bits and a label 21″ of p bits. Themonitoring and detection circuits (for example FIG. 3A or FIG. 7) checkthe configuration of at least one slice 20″a with at least twoconsecutive bits, generally an n-bit slice.

[0077] Similar to what is described above, at least one given bit of aslice is inverted when all of the bits are detected to be in the samelogical state “0” or “1.” The slice configurations are forced intopredetermined logical configurations as a function of this detection.The decoding is also performed in the way described in the case of“8B/10B” in the test of the configuration of the label. It follows thatit is also possible to perform additional tests by detectingnon-permitted logical configurations of the label. The latter, as afunction of its bit length, can have a set of possible logicalconfigurations. The authorized combinations form a first subset, and theunauthorized combinations form a second subset, the counterpart of thefirst. Finally, in the decoding, it is possible to test, when there hasbeen a bit inversion, whether all of the bit slices are in the samelogical state.

[0078] Through the reading of the above, it is easy to see that theinvention achieves the stated objects.

[0079] The method according to the invention specifically makes itpossible to guarantee:

[0080] a pre-established transition rate among all the bits constitutinga binary sequence;

[0081] a “Maximum Run Length (“MRL”) or maximum number or successivebits that can remain at the same logical value, “0” or “1”; and

[0082] a non-propagation of errors in the transmitted data.

[0083] In addition, according to a very advantageous characteristic,these properties are obtained using only very simple logical circuits,making it possible to accommodate many serial links in the same device,or even in the same integrated circuit (“chip”) card, withoutsubstantially increasing the production cost or the complexity.

[0084] It should be clear, however, that the invention is not limited tojust the exemplary embodiments explicitly described, particularly inconnection with FIGS. 3A through 8.

[0085] Nor is it limited, as indicated, to encoding of the “8B/10B” typealone.

1. Method for encoding/decoding digital data to be transmitted through aserial link, said digital data comprising a first so-called data bitsequence and a second so-called “label” bit sequence, characterized inthat, said first (20, 20′) and second (21, 21′) sequences having first(m) and second (p) given bit lengths, it includes at least one encodingphase comprising at least a step for checking (3, 3′, 9) at least oneslice (CDE, 20′a-20′b) of at least two consecutive bits, each of saidslices being located in a predetermined area of said first bit sequence(20, 20′), so as to create a partitioning of the latter into parts ofapproximately equal length, said check (3, 3′, 9) consisting ofperforming a test to determine whether the consecutive bits of each ofsaid slices (CDE, 20′a-20′b) are in the same logical state, “0” or “1,”a second step (7) consisting of setting the bits (X₁, X₂) of said secondsequence (21, 21′) to predetermined logical state configurations inone-to-one relation with the result of said test, and a step forinverting (4) at least one bit of said slices (CDE, 20′a-20′b) when theresult of said test is positive and for transmitting said first bitsequence (20, 20′) without any modifications when the result of saidtest is negative.
 2. Method according to claim 1, characterized in thatthe number of bits (p) in said second sequence is greater than or equalto the number of bits in said slices (n).
 3. Method according to claim1, characterized in that, said coding being the so-called “8B/10B” type,said first sequence (20) having a length of 8 bits so as to form a databyte wherein the successive positions (A . . . H) are numbered 1 through8, and said second sequence (21) having a length of 2 bits, it comprisesthe checking of a 3-bit slice (CDE) that includes bit number 5, and saidbits (X₁, X₂) of said second sequence (21) being set to the logicalconfiguration “01” when the result of said test is negative and in thelogical configuration “01” [sic] when the result of the test ispositive.
 4. Method according to claim 1, characterized in that itincludes a phase for decoding said encoded digital data comprising atleast one step for checking (8) the logical state configuration of thebits (X₁, X₂) of said second sequence and a step for selectivelyinverting at least one bit (D′) of said slices upon detection, duringsaid check, of predetermined logical configurations of said secondsequence, in order to re-establish said first sequence in its originalstate.
 5. Method according to claim 4, characterized in that, saidlogical configurations that can be assumed by the bits (X₁, X₂) of saidsecond sequence being included in a first subset of all the possiblecombinations permitted by the number of bits constituting this sequence,it includes a step for detecting non-permitted logical stateconfigurations, constituted by a second subset, the counterpart of thefirst, indicating at least one error occurring in said second sequence.6. Method according to claim 4, characterized in that when said step forchecking the logical state configuration of the bits (X₁, X₂) of saidsecond sequence indicates the presence of a bit inversion during theencoding, in at least one of said slices (CDE), it includes anadditional step (8 a) consisting, after decoding, of verifying that allthe bits of said slice are in the same logical state, “1” or “0.” 7.Device for encoding/decoding digital data to be transmitted through aserial link, said digital data comprising a first so-called data bitsequence and a second, so-called “label” bit sequence, characterized inthat, said first (20, 20′) and second (21, 21′) sequences having first(m) and second (p) given bit lengths, it comprises an encoder thatincludes at least one element (3, 3′, 9) for checking at least one sliceof at least two consecutive bits (CDE), each of said slices beinglocated in a predetermined area of said first bit sequence (20, 20′), soas to create a partitioning of the latter into parts of approximatelyequal length, said first element (3, 3′, 9) performing a test todetermine whether the consecutive bits of each of said slices are in thesame logical state, “0”or “1”, and delivering through its output (S, S″)a signal in a first given logical state when said test is positive an ina second given logical state when said test is negative, a secondelement (4) receiving the output signal (S, S″) from said first element(3, 3′, 9) through a first input and a given bit (D) of said slices(CDE) through a second input, so as to transmit it unchanged when saidtest is negative and to invert it when said test is positive, and athird element (7) driven by said output signal for generatingpredetermined logical configurations, in one-to-one relation.
 8. Deviceaccording to claim 7, characterized in that, said encoding being the“8B/10B” type, said first sequence (20) having a length of 8 bits so asto form a data byte (A . . . H) wherein the successive positions arenumbered 1 through 8, said second sequence (21) having a length of 2bits (X₁, X₂), and said slice (CDE) having a length of 3 bits, saidfirst element (3) comprises two “AND” logic gates (30, 31) in parallel,with three inputs, in order to receive through each of their inputs oneof the 3 bits of said slice (CDE) that includes bit number 5, and an“OR” logic gate (33) with two inputs, receiving the output signaldirectly from one of said “AND” logic gates (30) and receiving via aninverter (32) the output signal from the other of said “AND” logic gates(31), in order to deliver as output (S) a signal in the logical state“1” if, and only if, all the bits of said slice (CDE) are in the samelogical state, “0” or “1,” in that said second element is an“EXCLUSIVE-OR” logic gate (4) with two inputs, receiving through a firstinput the output signal (S) from said first element (3), and through asecond input the center bit (D) of said 3-bit slice (CDE), so as totransmit it unchanged when said test is negative and to invert it whensaid test is positive, and in that said third element comprises aninverter (7) receiving as input said output signal (S) from said firstelement (3), said second sequence being constituted by a first bit (X₁)in the same logical state as this signal (S) and a second bit (X₂) inthe same logical state as the output signal from said inverter (7). 9.Device according to claim 7, characterized in that it includes a decodercomprising at least one element for checking (8) the configuration ofthe bits (X₁, X₂) of said second sequence in order to selectively invertat least one bit (D′) of said slices upon detection of givenconfigurations indicating that this bit has been inverted during theencoding and to re-establish said first sequence in its original state.10. Device according to claim 9, characterized in that, said encodingbeing the so-called “8B/10B” type, said first sequence (20) having alength of 8 bits so as to form a data byte so as to form a data bytewherein the successive positions are numbered 1 through 8, said secondsequence (21) having a length of 2 bits, and said slice (CDE) having alength of 3 bits, said checking element (8) comprises an “AND” logicgate (80) having a direct input (801) and an inverting input (801)[sic], the bits (X₁, X₂) of said second sequence being transmitted tothese respective inputs, and an “EXCLUSIVE-OR” logic gate (81) with twoinputs, receiving through a first input (810) the output signal fromsaid “AND” logic gate (80), and through a second input (811) the centerbit (D′) of said three-bit slice, in order to transmit it unchanged whenthe logical configuration of said second sequence is “01” and to invertit when the logical configuration of said second sequence is “01” [sic].11. Device according to claim 9, characterized in that it includes afirst additional element for detecting errors in the configuration ofthe bits (X₁, X₂) of said second sequence (21) by detecting apredetermined logical configuration.
 12. Device according to claim 9,characterized in that it includes a second additional element (8 a) fordetecting an erroneous configuration of said slice (CDE) after decoding,when the logical configuration of the bits (X₁, X₂) of said secondsequence indicates that said bit has been inverted during said encoding,said erroneous configuration appearing when the 3 bits of said slice arein the same logical state.